Interrupts allow a processor to temporarily pause normal program execution and respond to an event. The distinction between vectored and non-vectored interrupts is mainly about how the processor determines the address of the interrupt service routine (ISR).
This difference affects hardware design, response time, software flexibility and how much work the programmer must do after an interrupt is accepted.
At a glance
| Point | Vectored interrupt | Non-vectored interrupt |
|---|---|---|
| ISR address | Predetermined or automatically obtained from a vector | Not inherently fixed for the interrupt source |
| Response path | Direct or near-direct jump to the handler | Often requires extra identification or dispatch logic |
| Software overhead | Usually lower at entry | Usually higher because the source may need to be identified |
| Flexibility | Vector assignments are constrained by the architecture/vector table | Can be flexible because software can decide how to dispatch |
| Hardware/software complexity | Architecture provides much of the routing mechanism | May require polling, external logic or shared-handler code |
| 8085 examples | TRAP, RST 7.5, RST 6.5 and RST 5.5 are commonly taught as vectored | INTR is the standard non-vectored example |
Vectored interrupt
A vectored interrupt gives the processor a specific interrupt vector or handler address. The vector may be fixed by the architecture or obtained through an interrupt-vector table.
Non-vectored interrupt
A non-vectored interrupt does not inherently point to one fixed ISR address. The system may jump to a common entry point and then identify the requesting device, or external hardware may supply instructions/address information.
How an interrupt is serviced
When an interrupt is accepted, the processor must save enough execution state to later resume the interrupted program. It then transfers control to interrupt-handling code. The key question is how it knows the address of that code.
With a vector, the destination is known from the architecture or vector table. Without one, another step is needed: the processor may acknowledge the interrupt, receive information from external hardware, or run a shared routine that polls devices.
Why vectors can improve response time
A vectored scheme reduces the amount of dispatch work after the interrupt occurs. That can make the path to the service routine shorter and more predictable, which is useful for time-sensitive events.
However, modern systems can implement both approaches efficiently. The practical performance depends on the processor’s interrupt controller, priority system, nesting rules, operating system and handler design.
8085 context
In 8085 coursework, the distinction is especially visible. TRAP and the RST 7.5/6.5/5.5 lines have defined vector locations. INTR is different: the external device participates in supplying an instruction during the interrupt-acknowledge sequence, so the interrupt itself does not have a single built-in vector address.
This is why exam questions often use the 8085 to illustrate the conceptual difference.
Frequently asked questions
Is every hardware interrupt vectored?
No. ‘Hardware interrupt’ describes the source/mechanism, while ‘vectored’ describes how the handler destination is determined.
Does vectored mean higher priority?
Not necessarily. Priority and vectoring are separate properties, although a processor may define both for particular interrupt lines.
Why are non-vectored interrupts still useful?
They can support flexible external interrupt hardware or shared interrupt lines where software identifies the source.
What is an interrupt vector table?
It is a table that associates interrupt identifiers with handler addresses. Many processors and operating systems use some form of vector table.
Sources and further reading
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